Circuit for controlling current flow through the heat sealing unit in a packaging apparatus

ABSTRACT

A circuit for controlling the duration and intensity of current flow through a resistive load, such as a heat sealing element in a plastic bag sealing apparatus. The circuit includes an inexpensive circuit for synchronizing the initiation of conduction of a triac or silicon-controlled rectifier with reversals in polarity of an alternating voltage source so that the load is supplied with a series of pulses of current each having the same magnitude and a circuit which is controlled by the synchronizing circuit and uses the reversals in flux in a transformer to decrease the duration of firing current pulses to a control electrode of the triac or silicon-controlled rectifier from a discharging capacitor.

United States Patent Inventor Dennis Burg Brown Deer, Wis.

Appl. No. 857,865

Filed Sept. 15, 1969 Patented June 29, 1971 Assignee Square D Company Park Ridge, [11.

CIRCUIT FOR CONTROLLING CURRENT FLOW THROUGH THE HEAT SEALING UNIT IN A Primary ExaminerDonald D. Forrer Assistant Examiner- David M. Carter Attorneys-Harold .l. Rathburn and William H. Schmeling ABSTRACT: A circuit for controlling the duration and intensity of current flow through a resistive load, such as a heat sealing element in a plastic bag sealing apparatus. The circuit includes an inexpensive circuit for synchronizing the initiation of conduction of a triac or silicon-controlled rectifier with reversals in polarity of an alternating voltage source so that the load is supplied with a series of pulses of current each having the same magnitude and a circuit which is controlled by the synchronizing circuit and uses the reversals in flux in a transformer to decrease the duration of firing current pulses to a control electrode of the triac or silicon-controlled rectifier from a discharging capacitor.

SOURCE CIRCUIT FOR CONTROLLING CURRENT FLOW THROUGH THE HEAT SEALING UNIT IN A PACKAGING APPARATUS The present invention relates to control circuits and is more particularly concerned with a circuit which will adjustably control the flow of energy from an alternating current source to a resistive load, such as the ribbon heater in a plastic bag sealing apparatus.

Apparatus as may be used to seal plastic bags frequently is provided with a resistive-type ribbon heater that is used for sealing the plastic packaging material and is sequenced through three distinct timing periods to accomplish the sealing operation. The timing periods which occur are: the preheat period, during which a low current is passed through the ribbon heater to preheat the ribbon; an impulse period, during which a high current is passed through the ribbon heater for a precisely controlled time to seal the plastic material; and an off time, which is provided to remove the sealed plastic material and reload the apparatus. To achieve a satisfactory seal without melting the sealed plastic material, it is required that both the duration and intensity of current flowduring the impulse period be accurately controlled. Further, as the current requirements of the ribbon heater are large, it is required that the signals initiating the conduction of the semiconductors controlling the current flow between an alternating current source and the ribbon heater be initiated precisely at an adjustable preselected point during each half cycle of the alternating current source, and have sufficient magnitude and duration so that the semiconductors will switch to a conductive state during each half cycle of the impulse period.

It is an object of the present invention to provide an inexpensive circuit for controlling the duration and intensity of current flow through a resistive load with a semiconductor that is switched into a conductive state at a precisely timed instant during each half cycle of an alternating current source for the load.

Another object is to provide a circuit for controlling current flow through a resistive load with an inexpensive synchronizing signal to delay the delivery of a pulse which switches a semiconductor into a conductive state so the semiconductor will conduct a precise portion of each half cycle of current flow from the source to the load.

An additional object is to provide a firing circuit for initiating the conduction ofa pair of silicon controlled rectifiers that are connected in an inverse parallel circuit between an alternating current source and a resistive load with a pair of capacitive circuits that are connected to opposite sides of the alternating current source through charging circuits each of which includes a primary winding of a transformer and a diode so that the capacitors are charged by a current flowing in one direction through the primary winding when the side of the source to which respective charging circuits are connected has a positive polarity, a separate discharge circuit for each capacitor with each discharge circuit including the primary winding and a silicon-controlled rectifier that is triggered into a conductive state to conduct current through the primary winding in a direction opposite the said one direction when the side of the source to which the charging circuit is connected has a negative polarity so that the cores of the respective transformers are driven toward saturation in opposite directions when the capacitors are charged and discharged and to rectifiers in both capacitive circuits with a common circuit that includes a transistor that is arranged to switch the siliconcontrolled rectifiers in the discharge circuits into conductive states at precise instants during appropriate half cycles of the alternating current supply so that the secondary windings of the transformers, which are connected to the gate electrodes of the appropriate inversely connected silicon-controlled rectifiers, will switch the inversely connected rectifiers into their conductive states.

initiate the conduction of the silicon controlled.

A further object is to provide a firing circuit for initiating the conduction of a triac-type semiconductor that is connected between an alternating current source and a resistive load with a pair of capacitive circuits that are connected to opposite sides of an alternating current source through diodes so that the capacitors are charged when the side of the source to which the respective charging circuits are connected has a positive polarity and a separate discharge circuit for each capacitor with each discharge circuit including a primary winding of a transformer and a silicon-controlled rectifier that is triggered into conduction by a circuit that is common to both capacitive circuits and includes a transistor that is arranged to switch the silicon-controlled rectifier into a conductive state at precise instants during the half cycles when the polarity of the side of the alternating current source to which the capacitive circuits that includes the triggered silicon-controlled rectifier has a negative polarity and to provide the transformer with a secondary winding that is connected to the gate electrode of the triac and to connect the primary windings that are included in the discharge circuits which are wound on the core of the transformer in a direction so the primary windings will induce flux in the core that have opposite directions when capacitors in the pair of capacitive circuits are discharged.

Further objects and features of the invention will be readily apparent to those skilled in the art from the specification and appended drawing illustrating certain preferred embodiments in which:

FIG. 1 is a wiring diagram schematically showing a control circuit for a resistive load incorporatingv the features'of the present invention.

Fig. 2 is a circuit schematic of a modified form of a portion of the circuit in FIG. 1 that controls the conduction of a triac in a resistive load circuit.

The control circuit as shown in FIG. 1 includes a synchronizing circuit 10, a timing circuit 12, a firing circuit 14, which provides pulses for switching a pair of semiconductors shown as a pair of silicon-controlled rectifiers l6 and 18 into conductive states, an initiating circuit 20 and an interval timing circuit 22. The silicon-controlled rectifiers 16 and 18 are connected in an inverse parallel circuit arrangement between an alternating current source 23 and a resistive load 24 which preferably consists of a ribbon heater portion of a plastic heat sealing apparatus. The control circuit also includes a suitable power supply including a transformer T having a primary winding TP energized by an alternating current source that is preferably, but not necessarily, the same source 23 that supplies the load 24. A secondary winding TS of the transformer T has a centertap 26 connected to a lead C that acts as a common or ground lead for the entire circuit. The power supply also includes suitable rectifiers and filters, not shown, for providing a direct current voltage output indicated as 20 volts DC at terminals 28, 30 and 32, as well as a potential of 12 v. DC at terminals 34 and 36. The secondary winding TS has a pair of output terminals 38 and 40 connected through diodes 42 and 44 to a terminal 46. The terminals 38 and 40 are also connected through a pair of leads 48 and 50 to a pair of terminals 52 and 54. The diodes 42 and 44 conduct whenever the terminals 38 and 40 have a positive polarity. Thus because the secondary winding TS has an alternating current output, at the beginning of each half cycle when the alternating current of the source 23 passes through zero, the potential at the terminal 46 will be zero and during all other periods will be a positive polarity potential.

The synchronizing circuit includes a transistor 56 having an emitter connected to the. lead C, a collector 57 connected through a load resistor R to the terminal 28 and a base connected through three load resistors R respectively to receive input signals from the terminal 46 through a lead 58, an input signal from a terminal 60 and an input signal through a lead 62 from the intervaltimingcircuit 22, as will be later described. The terminal 60 is respectively connected through a resistor 64 to the terminal 28, through a capacitor 66 to the lead C and through the normally open contacts of a switch 68 to the lead C.

The transistor 56, as well as certain other transistors in the circuit in FIG. I, are of the NPN type. As is well known, an NPN-type transistor will saturate when its base has a positive potential relative to its emitter and will desaturate when its base to emitter potential is zero or negative. Further, when the transistor is saturated, the potential at its collector becomes substantially equal to the potential of its emitter and will supply a signal which will hereinafter be designated as a signal. When the transistor is desaturated, the potential at its collector will approach the positive potential of the supply to which it is connected and will supply a signal which will hereinafter be designated as a l signal.

The synchronizing circuit operates as follows. When the contacts of the switch 68 are open, a continuous l signal, which is supplied to the base of the transistor 56 from the terminal 28 through the resistor 64 and the terminal 60, maintains the transistor 56 saturated so that a 0" output signal appears at the collector 57. The closure of the contacts of the switch 68 causes the current to the base of the transistor 56 that was supplied through the resistor 64 to be shunted to the lead C through the closed contacts of the switch 68. Thus the closure of the contacts of the switch 68 will cause a 0" signal to appear at the terminal 60. As will be later described, when the switch 68 is initially operated, the signal on lead 62 is 0". Thus when the contacts of the switch 68 are closed the conductive state of the transistor 56 is exclusively controlled by the signals appearing at the terminal 46. The terminal 46 is connected through the diodes 42 and 44 to receive the unfiltered full wave rectified output of the secondary winding TS. Thus the terminal 46 will provide a momentary 0 signal pulse to the base of the transistor 56 at the beginning of every half cycle of the alternating current source 23 when the polari ty of the source 23 reverses. The 0 signal pulse at the terminal 46 permits the transistor 56 to come out of saturation and causes a momentary l signal pulse to appear at the collector 57. The l output signal at the collector 57 disappears when the positive potential at the terminal 46 is reestablished. Thus the synchronizing circuit 10 operates to produce a l output signal pulse at the collector 57 at the beginning of every half cycle of the source 23 during periods when the switch 68 contacts are closed.

The timing circuit 12 includes a NPN-type transistor 72, a NPN-type transistor 74, a pair of PNP-type transistors 76 and 78, a timing capacitor 80, a pair of potentiometer-type resistors 82 and 84, a resistor 86, a pair of diodes 88 and 90 and a Zener type diode 92, together with the load resistors R that are connected in the base and collector circuits of the transistors 72 and 74. The transistors 72 and 74 each have their emitters connected to the lead C and their collector connected through load resistors R to the terminal 34. The base of the transistor 72 is respectively connected through load resistors R to the collector 57 of the transistor 56 and to the collector of the transistor 74. The base of the transistor 74 is connected to a terminal 94. The terminal 94 is connected to one side of the capacitor 80 which has its other side connected to the collector of the transistor 72. The Zener diode 92 is connected across the capacitor 80. The terminal 94 is also connected through the resistor 86 to a terminal 96. The transistors 76 and 78 each have their emitters connected to the terminal 34 and their collectors respectively connected through potentiometer resistors 82 and 84 to the terminal 96. The transistor 76 has a base connected through the diode 88 to the terminal 34 and through a resistor 98 to receive an output signal from the interval timing circuit 22, as will be later explained. The transistor 78 has a base connected through the diode 90 to the terminal 34 and through a resistor 100 to receive an output signal from the interval timing circuit 22, as will be later explained.

During the preheat period the timing circuit 12 operates as follows. As previously described, the closed contacts of the switch 68 will cause the collector 57 in the synchronizing circuit 10 to supply a momentary 1" output signal with each polarity reversal of the source 23. Also during the preheat period, the interval timing circuit 22 will supply signals through the resistors 98 and 100 which will cause the transistor 76 to be saturated and the transistor 78 to be desaturated. The saturated transistor 76 causes a positive polarity signal to be present at the terminal 94 which will cause the transistor 74 to be saturated and provide a 0" input signal to the base of the transistor 72 so that during the interval when the signal at the collector 57 is 0, the transistor 72 will be desaturated and supply a l signal at its collector. During the interval when the transistor 72 is desaturated, the capacitor will be charged to a voltage level determined by the breakover voltage of Zener diode 92 in a direction so that the side of the capacitor 80 that is connected to the collector of transistor 72 has a positive potential relative to the side of the capacitor 80 that is connected to the terminal 94. The momentary 1 signal pulse at the collector 57 which occurs each time the voltage of the source 23 passes through zero causes the transistor 72 to saturate so that a "0" signal appears at its collector and completes a discharge circuit for the previously established charge on the capacitor 80. The discharge path for the capacitor 80 includes the collector to emitter of the saturated transistor 72, the lead C, the supply that is connected between the lead C and the terminal 34, the emitter to collector of the saturated transistor 76, the resistor 82, the terminal 96, the resistor 86 and the terminal 94. The capacitor 80 discharges at a rate determined by the adjustment of the resistor 82. Also the switching of the transistor 72 to a saturated state causes the charge on the capacitor 80 to apply a reverse bias between the emitter to base of the transistor 74 which switches to a desaturated state and supplies a l signal at its collector. The l signal at the collector of the transistor 74 which is transmitted to the base of the transistor 72 maintains the transistor 72 in a saturated state after the momentary 1 pulse signal from the collector 57 disappears. The transistor 72 remains saturated and the transistor 74 desaturated during the interval required to discharge the capacitor 80 and recharge the capacitor in a direction so that the side of the capacitor 80 connected to the terminal 94 has a positive potential sufficient to bias the transistor 74 into saturation. The saturated transistor 74 removes the l signal to the base of the transistor 72 which again switches to a desaturated state and permits the capacitor 80 to be recharged. In the embodiment shown, the RC constants of the circuit are selected so that the capacitor 80 will discharge and the transistor 74 will saturate an adjustable interval of 1.0 to 7.3 milliseconds after the synchronizing circuit 10 has supplied an input signal of 1" to the transistor 72. Thus a predetermined interval, as determined by the adjustment of the resistor 82, during each half cycle of the source 23, the transistor 74 in the timing circuit 12 will supply a signal which changes from a l to a 0 at its collector electrode A capacitor 102 is connected between the collector of the transistor 74 and a base of a transistor 104 in the firing circuit 14. A resistor 106 is connected across the capacitor 102 and a resistor 108 is connected between the terminal 34 and the side of the capacitor 102 that is connected to the base of the transistor 104. During the intervals when the signal at the collector of the transistor 74 is 0", the capacitor 102 will be discharged and the transistor 104 will be saturated by a current flow from the terminal 34 through the resistor 108. As previously described, at the beginning of each half cycle of the source 23, the signal at the collector of the transistor 74 changes from 0 to 1". The change to a l signal at the collector of the transistor 74 charges the capacitor 102 in a direction making the side of the capacitor 102 that is connected to the collector of the transistor 74 positive in polarity. A predetermined interval after the beginning of each half cycle of the source 23, the signal at the collector of the transistor 74 changes from 1 "to 0". The change from a l to a 0" signal at the collector of the transistor 74 causes the capacitor 102 to discharge through a circuit which includes the collector to emitter of the transistor 74, the lead C, the supply which is connected between the lead C and the terminal 34, the terminal 34 and the resistor 108. In a preferred embodiment, the RC constants are selected so that the discharge of the capacitor 102 causes the base to emitter current through the transistor 104 to be removed for approximately 300 microseconds after the signal at the collector of the transistor 74 has changed from a 1 to 0", at which time the transistor 104 again saturates in response to the discharged capacitor 102 and the current flow through the resistor 108. Thus for approximately 300 microseconds after the timing circuit 12 has timed out, the transistor 104 will be desaturated and cause a l signal to appear at its collector.

The firing circuit 14 includes the terminals 32, 52 and 54, the transistor 104, a pair of capacitors 110 and 112, a pair of capacitors 114 and 116, a pair of capacitors 118 and 120, a pair of silicon controlled rectifiers 122 and 124, a pair of diodes 126 and 128, a pair of diodes 130 and 132, a pair of diodes 134 and 136, a pair of resistors 138 and 140, a pair of resistors 142 and 144, a pair of resistors 146 and 148, a pair of resistors 150 and 152, a pair of resistors 154 and 156, a resistor 158 and a pair of transformers 160 and 162 each having a magnet iron core. The transformer 160 has a primary winding 164 and a secondary winding 166 wound on its core. Similarly, the transformer 162 has a magnet iron core with a primary winding 168 and a secondary winding 170 wound on its core. The components of the firing circuit 14 are connected to operate as follows.

During the intervals when the transistor 104 is saturated and the half cycles of the source 23 causes the terminal 52 to have a positive potential with respect to the lead C and the terminal 54 to have a negative potential with respect to the lead C, the positive potential at the terminal 52 will cause current to flow through the diode 126, the resistor 138, a terminal 172 and the primary winding 164 to charge the capacitor 110 to a positive potential. As a result of the charging current for the capacitor 110, the flux in the iron core of the transformer 160 will be driven toward saturation on one direction on its hysteresis loop. The capacitor 114 will also be charged by the current flow through the diode 126. However, as the purpose of the capacitor 114 is to suppress noise in the anode circuit of the silicon controlled rectifier 122, its presence in the circuit will not be further discussed. The diode 136, which is also connected to the terminal 52, is reversed biased when the terminal 52 has a positive polarity so that no current will flow through the diode 136. During intervals when the terminal 52 has a positive polarity and the terminal 54 has a negative polarity with respect to the lead C, the diode 134 will be forward biased and permit current to flow from the lead C through the resistor 146 or the diode 130, a terminal 174, the resistor 142 and the diode 134 to the terminal 54 which causes a negative voltage to appear at the gate of the rectifier 122 which prevents the rectifier 122 from conducting. The capacitor 118 is included in the circuit to suppress noise in the gate circuit of the rectifier 122.

During the intervals when the transistor 104 is saturated and the half cycles of the source 23 cause the terminal 54 to have a positive potential with respect to the lead C and the terminal 52 to have a negative potential with respect to the lead C, the positive potential at the terminal 54 will cause current to flow through the diode 128, the resistor 140, a terminal 176 and the primary winding 168 to charge the capacitor 112 to a positive potential. As a result of the charging current for the capacitor 112, the flux in the iron core of the transformer 162 will be driven toward saturation on one direction on its hysteresis loop. The capacitor 116 will also be charged by the current flow through the diode 128. However, as the purpose of the capacitor 116 is to suppress noise in the anode circuit of the silicon controlled rectifier 124, its presence in the circuit will not be further discussed. The diode 134, which is also connected to the terminal 54, is reversed biased when the terminal 54 has a positive polarity so that no current will flow through the diode 134. During intervals when the terminal 54 hasa positive polarity and the terminal 52 a negative polarity with respect to the lead C, the diode 136 will be forward biased and permit current to flow from the lead C through the resistor 148 or the diode 132, a terminal 178, the resistor 144 and the diode 136 to the terminal 52 which causes a negative voltage to appear at the gate of the rectifier 124 which prevents the rectifier 124 from conducting. The capacitor is included in the circuit to suppress noise in the gate circuit of the rectifier 124.

As was previously described, the closure of the contacts of the switch 68 causes the transistor 104 to desaturate for a brief interval after a predetermined instant during each half cycle of the source 23. When the transistor 104 desaturates and the terminal 52 is positive relative to the lead C, the potential at the collector of transistor 104 will be substantially equal to the potential of the terminal 32 and the diode 136 will be reversed biased. This condition will cause current to flow from the terminal 32, through the resistor 158, the resistor 152, the resistor 144, the terminal 178 and through the gate to cathode of the rectifier 124 which triggers the rectifier 124 into conduction. The conducting rectifier 124 causes the energy stored in the capacitor 112 to be discharged through a circuit including the primary winding 168, the resistor 156, and the anode to cathode of the rectifier 124. The resistor 156 limits the discharging current of the capacitor 112 through the discharge circuit. It is to be noted that the direction of the current flow through the primary winding 168 during the discharge of the energy stored within the capacitor 112 is opposite the direction of current flow when the capacitor 112 was charged. Thus during the discharge of the capacitor 112, the flux in the core of the transformer 162 will be driven toward saturation in a direction on its hysteresis loop that is opposite the direction in which it was driven when the capacitor 112 was being charged and will result in a wider pulse output of the secondary winding 170 which results from the discharge current from the capacitor 112.

When the discharge current from the capacitor 112 through the rectifier 124 becomes less than the holding current of the rectifier 124, the rectifier 124 ceases to conduct and reverts to its blocking state as current cannot be supplied to the rectifier 124 through the diode 128 and the resistor 140 because the terminal 54 has a negative polarity during the half cycle when the rectifier 124 is switched to a conductive state to provide a discharge path for the capacitor 112. During the succeeding half cycle when the terminal 54 has a positive polarity, current will again flow through the diode 128, the resistor 140, the terminal 176 and the primary winding 168 to recharge the capacitor 112.

During the half cycles that the terminal 54 has a negative polarity, the gate of the rectifier 122 will be reversed biased due to the current flowing from the lead C through the diode 130, the terminal 174, the resistor 142 and the diode 134. The diode limits the reverse bias to the gate of the rectifier 122 to the forward voltage drop across the diode 130. The resistor 146 is connected across the gate to cathode junctions of the rectifier 122 to improve the dv/dt capabilities of the rectifier 122 in the circuit.

It will be seen that during the interval when the current flowing through the collector and emitter of the transistor 104 is providing a triggering current to the gate of the rectifier 124, current will also flow through the resistor 158, the resistor 150, the diode 134 to the terminal 54. The current flow through this circuit will tend to reduce the drive to the gate of the rectifier 124 and can be minimized by proper selection of the resistance value of the resistors 150, 152 and 158.

When the transistor 104 desaturates and the terminal 54 is positive relative to the common lead C, the potential at the collector of transistor 104 will be substantially equal to the potential of the terminal 32 and the diode 134 will be reversed biased. This condition will cause current to flow from the terminal 32 through the resistor 158, the resistor 150, the resistor 142, the terminal 174 and through the gate to cathode of the rectifier 122 which triggers the rectifier 122 into conduction.

The conducting rectifier 122 causes the energy stored in the capacitor 110 to be discharged through a circuit including the primary winding 164, the resistor 154, and the anode to cathode of the rectifier 122. The resistor 154 limits the discharging current of the capacitor 110 through the discharge circuit. It is to be noted that the direction of current flow through the primary winding 164 during the discharge of the energy stored within the capacitor 110 is opposite the direction of current flow when the capacitor 110 was charged. Thus during the discharge of the capacitor 110, the flux in the core of the transformer 160 will be driven toward saturation in a direction on its hysteresis loop that is opposite the direction in which it was driven when the capacitor 110 was being charged and will result in a wider pulse output of the secondary winding 166 which results from the discharge current from the capacitor 110.

When the discharge current from the capacitor 110 through the rectifier 122 becomes less than the holding current of the rectifier 122, the rectifier 122 ceases to conduct and reverts to its blocking state as current cannot be supplied to the rectifier 122 through the diode 126 and the resistor 138 because the terminal 52 has a negative polarity during the half cycle when the rectifier 122 is switched to a conductive state to provide a discharge path for the capacitor 110. During the succeeding half cycle when the terminal 52 has a positive polarity, current will again flow through the diode 126, the resistor 138, the terminal 172 and the primary winding 164 to recharge the capacitor 110.

During the half cycles that the terminal 52 has a negative polarity, the gate of the rectifier 124 will be reversed biased due to the current flowing from the lead C through the diode 132, the terminal 178, the resistor 144 and the diode 136. The diode 132 limits the reverse bias to the gate of the rectifier 124 to the forward voltage drop across the diode 132. The resistor 148 is connected across the gate to cathode junctions of the rectifier 124 to improve the dv/d! capabilities of the rectifier 124 in the circuit.

1! will be seen that during the interval when the current flowing through the collector and emitter of the transistor 104 is providing a triggering current to the gate of the rectifier 122, current will also flow through the resistor 158, the resistor 152, the diode 136 to the terminal 52. The current flow through this circuit will tend to reduce the drive to the gate of the rectifier 122 and can be minimized by the proper selection of the resistance value of the resistors 150, 152, and 158.

The secondary windings 166 and 170 are respectively connected to the gates and cathodes of the rectifiers 16 and 18 in a direction so that the output current pulse which occurs when the capacitors 110 and 112 are discharged will be in a direction which will cause the rectifiers 16 and 18 to switch into a conductive state during the half cycles of the source 23 when the respective anodes of the rectifiers 16 and 18 are positive in polarity. Thus because of the resetting of the flux within the cores of the transformers 160 and 162 as previously described, the gates of the rectifiers 16 and 18 will receive a pulse of current that has a duration which will assure the switching of the rectifiers l6 and 18 into their conductive states during each half cycle. lt is well known that after a silicon controlled rectifier has been switched into a conductive state by a current pulse on its gate, the silicon controlled rectifier will continue to conduct as long as its anode has a positive potential relative to its cathode even though the switching current to its gate is removed. Thus after the switching pulse is supplied to the gates of the rectifiers 16 and 18, the rectifiers l6 and 18 will continue to conduct current through the load 24 during the remainder of the half cycles of the source 23.

The initiating circuit 20 includes a transistor 180 having an emitter connected to the lead C, a collector 182 connected through a load resistor R to the terminal 30 and a base connected through four load resistors R respectively to receive input signals from the terminal 46 through a lead 184, an input signal from a terminal 186, an input signal from a terminal 188 and an input signal through a lead 190 from the interval timing circuit 22, as will be later described. The terminal 186 is connected through a resistor 192 to the terminal 30. The terminal 188 is respectively connected through the terminal 186 and the resistor 192 to the terminal 30, through a resistor 189 and a capacitor 194 to the lead C and through the normally open contacts ofa switch 196 to the lead C.

The initiating circuit 20 operates as follows. When the contacts of the switch 196 are open, a continuous I signal, which is supplied to the base of the transistor from the terminal 30 through the resistor 192 and the terminals 186 and 188, maintains the transistor 180 saturated so that a 0" output signal appears at the collector 182. The closure of the contacts of the switch 196 causes the current to the base of the transistor 180 that was supplied through the resistor 192 and the terminals 186 and 188 to be shunted to the lead C through the closed contacts of the switch 196. Thus the closure of the contacts of the switch 196 will cause a 0 signal to appear at the terminals 186 and 188. As will be later described, when the switch 196 is initially operated, the signal on lead is 0. Thus when the contacts of the switch 196 are closed, the conductive state of the transistor 180 is exclusively controlled by the signals appearing at the terminal 46. The terminal 46 is connected through the diodes 42 and 44 to receive the unfiltered full wave rectified output of the secondary winding TS. Thus the terminal 46 will provide a momentary 0" signal pulse to the base ofthe transistor 180 at the beginning of every half cycle of the alternating current source 23 when the polarity of the source 23 reverses. The 0 signal pulse at the terminal 46 permits the transistor 180 to come out of saturation and causes a momentary l signal pulse to appear at the collector 182. The 1" output signal at the collector 182 disappears when the positive potential at the terminal 46 is reestablished. Thus the initiating circuit 20 operates to produce a 1 output signal pulse at the collector 182 at the beginning of every half cycle of the source 23 during periods when the switch 196 contacts are closed and a 0" signal is supplied by the lead 190 to the base of the transistor 180.

The interval timing circuit 22 includes NPN-type transistors 198,200,202, 204 and 206, each having an emitter connected to the lead C.

The transistors 198 and 200 each have a collector connected through a load resistor R to the terminal 36 and the transistors 202, 204, and 206 each have their collectors connected through a load resistor R to the terminal 30. The collector 182 supplies an input through a load resistor R to the base of the transistor 198. The collector of the transistor 198 supplies an input through a load resistor R to the base of the transistor 200 and is connected to one side of a capacitor 208 which has its other side connected to a terminal 210. The terminal 210 is connected through a resistor 212 and an adjustable resistor 213 to the terminal 36 and to the base of the transistor 200. The collector of the transistor 200 is connected through suitable load resistors R to supply inputs to the bases of the transistors 198, 202 and 206. The collector of the transistor 202 is connected through a load resistor R to supply an input to the transistor 204, through the resistor 100 to supply an input to the base of the transistor 78 and through a load resistor R to supply an input to the base of the transistor 206. The collector of the transistor 204 is connected to supply an input through the lead 190 to the base of the transistor 180, an input through the resistor 98 to the base of the transistor 76 and an input through a load resistor R to the base of the transistor 202.

The interval timing circuit 22 operates as follows. During the interval the contacts of the switch 196 are open, as previously described, the initiating circuit 20 will cause a continuous 0 signal to appear at the collector 182 which is supplied to the base of the transistor 198 and a continuous 1 signal at the terminal 188 which is supplied to the base of the transistor 204. The transistor 198 also receives a 0 signal at its base from the collector of the transistor 200. Thus as both inputs to the base of the transistor 198 are 0", the transistor 198 will be desaturated and provide a l output signal at its collector which is supplied as an input to the base of the transistor 200 and causes the transistor 200 to saturate and have a output signal. During the interval when the collector of the transistor 198 has a l output signal, the capacitor 208 will be charged in a direction so that the side of the capacitor 208 that is connected to the collector of the transistor is positive in polarity relative to the side of the capacitor 208 that is connected to the terminal 210. Note when power is initially applied to the circuit, the transistor 200 will be driven into a saturated condition by the current flow through its base which initially is required to charge the capacitor 208, and during the period the charge on the capacitor 208 is being established, the transistor 200 will be biased into saturation by the current flow through the resistors 213 and 212. The 0" output signal at the collector of the transistor 200 causes the transistor 202 to be desaturated and provide a l output signal at its collector. The collector of the transistor 202 is connected through a load resistor R to the terminal 30 which has a positive potential of 20 VDC impressed thereon. The emitter of the transistor 78 in the timing circuit 12 is connected to the terminal 34 which has a positive polarity of 12 v. DC impressed thereon. Thus in spite of the fact that the collector of the transistor 202 has a l output signal, the transistor 78 will be back-biased into a desaturated condition. The l output signal at the collector of the transistor 202 also causes the transistors 204 and 206 to be saturated and provide a 0" output signal at their respective collectors. The 0" output signal at the collector of the transistor 204 is supplied to the lead 190 as previously described, and as supplied through the resistor 98 to the base of the transistor 76 permits the transistor 78 to be saturated and complete a charging circuit for the capacitor 80 in the timing circuit 12, as was previously described. The 0 output signal at the collector of the transistor 206 as transmitted through the lead 62 does not influence the conductive state of the transistor 56 in the synchronizing circuit 10, as was previously described The impulse period is initiated when a suitable timing means, not shown, closes the contacts of the switch 196 and maintains the contacts of the switch 68 closed. The closed contacts of the switch 196 causes the removal of the 1" signal at the terminals 186 and 188 so that the conductive condition of the transistor 180 is exclusively controlled by the signals appearing on the lead 190 and the terminal 46. The removal of the l signal to the base of the transistor 204 is without effect as the transistor 204 remains saturated because of the l output signal from the transistor 202. Therefore the signal on the lead 190 remains 0" so that the conductive state of the transistor 180 is exclusively controlled by the signals appearing at the terminal 46. As previously described, the signals at the terminal 46 cause the collector 182 to provide a momentary l signal pulse at the beginning of each half cycle of the source 23. The l signal pulse at the collector 182 causes the transistor 198 to saturate and complete a discharge circuit for the charge on the capacitor 208 through a circuit that includes the collector to the emitter of the transistor 198, the lead C, the supply that is connected between the lead C and the terminal 36, the terminal 36, the adjustable resistor 213, the resistor 212 and the terminal 210. The rate of discharge of the capacitor 208 and therefore the duration of the impulse time period is controlled by the RC constants of the discharge circuit and can be varied by changing the resistance value of the adjustable resistor 213. The discharge of the capacitor 208 also causes the transistor 200 to desaturate and supply a l output signal at its collector. The l output signal from the transistor 200 is supplied as an input to the bases of the transistors 198, 202 and 206. Thus during the interval when the capacitor 208 is discharging, the transistor 198 will be maintained saturated independently of the 0" to l signal changes at the collector 182. The l signal output from the transistor 200 will maintain the transistor 206 saturated independently of the signals appearing at the collector of the transistor 202 so that the switching to a saturated state of the transistor 202 will not effect the saturated state of the transistor 206. The 1 signal output of the transistor 200 will cause the transistor 202 to be saturated and supply a 0" signal at its collector, The 0" signal at the collector of the transistor 202 causes the transistor 204 to desaturate and supply a 1 output signal at its collector. The 1 output signal at the collector of the transistor 204 as transmitted by the lead 190 maintains the transistor 180 saturated so even though the contacts of the switch l96are closed, further pulsing l signals will not appear at the collector 182. The collector of the transistor 204 is connected to a v. DC

. supply at the terminal and the emitter of the transistor 76 is connected to a 12 v. DC supply at the terminal 34. Thus the 1" signal atthe collector of the transistor 204 will back-bias the transistor 76 and cause the transistor 76 to desaturate and interrupt the charging circuit through the transistor 76 for the capacitor 80 in the timing circuit 12. The 0" output signal at the collector of the transistor 202 permits the transistor 78 to saturate and complete a discharging circuit for the capacitor 80-through the adjustable resistor 84. in the same manner as the adjustable resistor 82 controlled the discharging circuit when the transistor 76 was saturated. The RC constants of the circuit including the transistor 76 and the adjustable resistor 84 are selected so that the capacitor 80 will discharge more rapidly when the transistor 78 is saturated than when the transistor 76 is saturated. Thus as the synchronizing circuit causes the capacitor 80 to begin discharging at the beginning of each half cycle of the source 23 and the firing circuit 14 causes the rectifiers l6 and 18 to switch to conductive states when the capacitor 80 has discharged to a predetermined value, the rectifiers l6 and 18 will switch to their conductive states earlier during each half cycle of the source 23 during the impulse period and the load 24 will be supplied with greater electrical energy during theimpulse period than during the preheat period.

The impulse period ends when the charge on the capacitor 208 becomes insufficient to maintain the transistor 200 in a desaturated condition. If the switches 68 and 196 are closed at the end of the impulse period, the following conditions will prevail within the circuit. The transistor 200 will be saturated by a base current flow through the resistors 213 and 212 and supply a 0" output signal. The closed switch 196 will cause a 0" input signal to be delivered to the base of the transistor 204 which is connected with the transistor 202 as a logic memory. Thus the change to a 0" output signal of the transistor 200 will not cause the transistors 202 and 204 to switch their conductive states and the output signal of the transistor 202 will continue as a 0 and the output signal of the transistor 204 will continue as a 1. The 1 output signal of the transistor 204 as transmitted by the lead 190 to the transistor will cause the transistor 180 to have a continuous 0 output signal. Thus as both the inputs to the transistor 198 from the transistors 180 and 200 are 0," the transistor 198 will have a 1" output signal and the capacitor 208 will charge in the manner previously described. The 0" output signals of the transistors 200 and 202 as impressed on the base of the transistor 206 will cause the transistor 206 to desaturate and supply a 1" input signal through the lead 62 to the transistor 56 in the synchronizing circuit 10 which will prevent the transistor 56 from supplying signal pulses which cause the timing circuit 12 and the firing circuit 14 to switch the rectifiers l6 and 18 to their conductive states. The timing means, not shown, preferably is arranged to open the contacts of the switch 68 before the contacts of the switch 196 are opened. The opening of the contacts of the switch 68 when the contacts of the switch 196 are closed at the end of the impulse period does not change the conductive state of the synchronizing circuit 10 because of the l input signal on the lead 62 from the transistor 206. The opening of the contacts of the switch 196 causes a 1" input signal to be delivered to the base of transistor 204 which resets the logic memory consisting of the transistors 202 and 204 so that the transistor 204 is saturated and the transistor 202 is desaturated. The desaturated transistor 202 supplies a 1 input signal to the transistor 206 which causes the transistor 206 to saturate and remove the blocking l signal via lead 62 to the transistor 56 so the synchronizing circuit is restored to the condition previously described when the switch 68 was open. The resetting of the logic memory consisting of the transistors 204 and 202 causes the transistor 76 to be saturated and the transistor 78 to be desaturated as previously described so the timing circuit is restored to operate and time the preheat current pulses to the load 24 as previously described.

A firing circuit 214, shown in FIG. 2, is similar to the firing circuit 14 shown in FIG. 1, except that the circuit shown in FIG. 2 is intended to switch a solid state semiconductor device known as a triac into a conductive state and the circuit in FIG. 1 supplies firing pulses for switching a pair of silicon-controlled rectifiers into conductive states. Therefore the components which are identical and function in the same manner in the circuits shown in FIG. 1 and FIG. 2 are identically designated.

The triac firing circuit shown in FIG. 2 differs from the firing circuit shown in FIG. I only in the type of pulse transformers used in the circuits and the manner in which they are connected in the circuits. The triac firing circuit shown in FIG. 2 uses a single transformer having a pair of primary windings 218 and 220 and a single secondary winding 222 wound on a common magnet iron core 224, as indicated by the broken line in FIG. 2. The firing circuit shown in FIG. 1 uses a pair of transformers each having a single primary winding and a single secondary winding wound on the common core. In view of the previous description of the operation of the circuit shown in FIG. 1, the operation of the circuit shown in FIG. 2 will be apparent from the following description.

During intervals when the terminal 52 has a positive polarity relative to the terminal 54, charging current for the capacitor 110 will flow through the diode 126, the resistor 138, the terminal 172 in a direction making the side of the capacitor that is connected to the terminal 172 positive in polarity. Current will also flow through the diode 126, the resistor 138, the terminal 172 and the primary winding 218 to charge the capacitor 114. The primary purpose of the capacitor 114 is to suppress noise in the anode circuit of the rectifier 122 and its capacitance value is small. Therefore the charging current to the capacitor 114 through the primary winding 218 will be insufficient to cause a change in the state of the flux in the core 224. At some instant during the next cycle of the source 24 after the capacitor 1110 has been charged when the terminal 54 is positive in polarity relative to the terminal 52 and the rectifier 122 is triggered into a 'conductive state as previously described, the capacitor 110 will discharge through the following circuit. The discharge circuit for the capacitor includes the terminal 172, the primary winding 218, the resistor 154 and the conducting rectifier 122. The discharging current provided by the capacitor 110 through the primary winding 218 causes the secondary winding 222 to provide an output current pulse which has a polarity making the dotted end of the secondary winding 222 positive relative to the undotted end. After the discharging current from the secondary winding 222 ceases to .flow, a certain amount of residual flux will remain stored in the core 224 of the pulse transformer.

As also previously described, during the half cycle that the capacitor 110 is being discharged, the capacitor 112 is charged from the terminal 54 through the rectifier 128, the resistor 140 and the terminal 176. During the subsequent half cycle when the rectifier 124 is switched to a conductive state as previously described, the capacitor I 112 will discharge through the primary winding 220. The discharging current through the primary winding 220 provided by the capacitor 112 causes a current pulse to be produced in the secondary winding 222 which has a polarity making the undotted end of the secondary winding 222 positive with respect to the dotted end of the secondary winding 222. Thus when capacitor 110 is discharged, the polarity of the pulse induced in the secondary winding 222 will be opposite the polarity when the capacitor 112 is discharged. The secondary winding 222 is connected between the gate electrode and one of the main electrodes of a triac 226. Thus the pulse produced in the secondary winding by the discharged capacitors and 112 will be alternately positive and negative and be compatible in the manner in which triacs may be most advantageously fired. Further, because of the alternate pulsing of the primary windings 218 and 220 in the transformer, the discharge current of the capacitors 1 10 and 112 will always be in a direction to oppose the residual flux which was stored in the .core 224 of the transformer from the previous half cycle discharge and will thus reset the core 224 so that the secondary winding 222 will provide output pulses having an appreciable duration to assure switching of the triac 226 into a conductive state.

While certain preferred embodiments of the invention have been specifically disclosed, it is understood that the invention is not limited thereto, as many variations will be readily apparent to those skilled in the art and the invention is to be given its broadest possible interpretation within the terms of the following claims.

What 1 claim is:

l. A circuit for controlling current flow through a resistive load from an alternating current source comprising: a synchronizing circuit including a transistor having an input connected to the source and an output connected to supply an output signal at each instant the alternating current of the source reverses, a timing means having an input connected to receive the output signal from the synchronizing circuit and provide an output signal a preselected time interval during each half cycle of alternating current flow subsequent to the receipt of an output signal from the synchronizing circuit, and firing means having an input connected to receive the output signal from the timing means and provide output signals for al ternately switching a pair of power circuit type silicon-controlled rectifiers that are connected in inverse parallel between the source and the load into conductive states in response to an output signal from the timing means, said firing means including, a pair of output signal pulsing circuits with a first of said pair of pulsing circuits including a first capacitor, a first silicon-controlled rectifier having a pair of main electrodes and a gate electrode, a first transformer having a primary winding connected in a series circuit with the first capacitor and the main electrodes of the first silicon-controlled rectifier and a secondary winding coupled through a magnet iron core to the primary winding and connected to the gate electrode and the cathode of a first one of the pair of power circuit type silicon-controlled rectifiers, and a circuit including a diode and the primary winding of the first transformer for charging the first capacitor from the source with a pulse of current that flows in one direction through the primary winding of the first transformer when a first side of the source has a positive polarity, a second of said pair of pulsing circuits including, a second capacitor, a second silicon-controlled rectifier having a pair of main electrodes and a gate electrode, a second transformer having a primary winding connected in a series circuit with the second capacitor and the main electrodes of the second silicon-controlled rectifier and a secondary winding coupled through a magnet iron core to the primary winding and connected to the gate electrode and the cathode of a second one of the pair of power circuit type silicon-controlled rectifiers, and a circuit including a diode and the primary winding of the second transformer for charging the second capacitor from the source with a pulse of current that flows in one direction through the primary winding of the secondtransformer when a second side of the source has a positive polarity, and a commutating circuit means including a transistor having its conductive state controlled by the output signal from the timing means and connected to the gate electrodes of the silicon-controlled rectifiers in the first and the second pair of pulsing circuits for switching the first siliconcontrolled rectifier to a conductive state for discharging the first capacitor through the primary winding of the first transformer in a direction opposite the said one direction and thereby providing a firing pulse to the first power circuit type silicon-controlled rectifier when the second side of the source has a positive polarity and for switching the second siliconcontrolled rectifier to a conductive state for discharging the second capacitor through the primary winding of the second transformer in a direction opposite the said one direction and thereby providing a firing pulse to the second power circuit type silicon-controlled rectifier when the first side of the source has a positive polarity.

2. A circuit for controlling current flow through a resistive load from an alternating current source comprising; a synchronizing circuit including a transistor having an input connected to the source and an output connected to supply an output signal at each instant the alternating current of the source reverses, a timing means having an input connected to receive the output signal from the synchronizing circuit and providing an output signal a preselected time interval during each half cycle of alternating current flow subsequent to the receipt of an output signal from the synchronizing circuit, a firing means having an input connected to receive the output signal from the timing means and providing output signals for switching a triac-type semiconductor device that has a pair of main electrodes connected in a series circuit between the and the load into a conductive state in response to the output signals from the timing means, said firing means including, a transformer having a first primary winding, a second primary winding and a secondary winding wound on a common core with the secondary winding connected between one of the main terminals and a gate electrode of the triac, a pair of pulsing circuits with a first of said pair of pulsing circuits including, the first primary winding, a first capacitor, a first silicon-controlled rectifier having a gate electrode and a pair of main electrodes, a circuit excluding the first primary winding and including a diode for charging the first capacitor from the source with a pulse of current when a first side of the source has a positive polarity, and a circuit including the first capacitor, the first primary winding and the main electrodes of the first silicon-controlled rectifier for discharging the first capacitor through the first primary winding and the first silicon-controlled rectifier with a current flow tending to saturate the core in one direction upon conduction of the first silicon-controlled rectifier, a second of said pair of pulsing circuits in- 5 cluding, the second primary winding, a second capacitor, a

second silicon-controlled rectifier having a gate electrode and a pair of main electrodes, a circuit excluding the second primary winding and including a diode for charging the second capacitor from the source with a pulse of current when a second side of the source has a positive polarity, and a circuit including the second capacitor, the second primary winding and the main electrodes of the second silicon-controlled rectifier for discharging the second capacitor through the second primary winding and the second silicon-controlled rectifier with a current flow tending to saturate the core in a direction opposite the said one direction upon conduction of the second silicon-controlled rectifier, and circuit means including a transistor having its conductive state controlled by the output signal from the timing means and connected to the gate electrodes of the silicon-controlled rectifiers in the said first and the second pair of pulsing circuits for switching the first siliconcontrolled rectifier to a conductive state for discharging the first capacitor through the through the first primary winding and causing the secondary winding to provide a pulse of current between the gate and the said one main terminal of the triac that flows in one direction when the second side of the source has a positive polarity and for switching the second silicon-controlled rectifier to a conductive state for discharging the second capacitor through the second primary winding and causing the secondary winding to provide a pulse of current between the gate and the said one main terminal of the triac that flows in a direction opposite the said one direction when the first side of the source has a positive polarity.

3. The circuit as recited in claim 1 wherein the synchronizing circuit includes an actuatable means connected to the input of the transistor to prevent the synchronizing circuit from supplying the output signal when the actuatable means is deactivated.

4. The circuit as recited in claim 1 wherein the gate electrode of the first silicon-controlled rectifier is connected through a first diode to the second side of the source and the gate electrode of the second silicon-controlled rectifier is connected through a second diode to the first side of the supply and said first and second diodes being connected to the transistor in the commutating circuit and poled in a direction to cause the first silicon-controlled rectifier to switch to a conductive state when the first side of the source has a negative polarity and to cause the second silicon-controlled rectifier to switch to a conductive state when the second side of the source has a negative polarity.

5. The circuit as recited in claim 2 wherein the synchronizing circuit includes an actuatable means connected to the input of the transistor to prevent the synchronizing circuit from supplying the output signal when the actuatable means is deactivated.

6. The circuit as recited in claim 2 wherein the gate electrode of the first silicon-controlled rectifier is connected through a first diode to the second side of the source and the gate electrode of the second silicon-controlled rectifier is connected through a second diode to the first side of the supply and said first and second diodes being connected to the transistor in the commutating circuit and poled in a direction to cause the first silicon-controlled rectifier to switch to a conductive state when the first side of the source has a negative polarity and to cause the second silicon-controlled rectifier to switch to a conductive state when the second side of the source has a negative polarity.

7. The circuit as recited in claim 1 wherein the timing means includes a pair of timing circuits which are selectively programmed so that the timing means will provide an output signal at either of two different time intervals during each half cycle subsequent to the receipt of an output signal from the synchronizing circuit.

8. The circuit as recited in claim 2 wherein the timing means includes a pair of timing circuits which are selectively programmed so that the timing means will provide an output signal at either of two different time intervals during each half cycle subsequent to the receipt of an output signal from the synchronizing circuit.

mg UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,59 7 Dated June 29, 97

Inventor(s) nis Burg It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

C01. 9, line 6, after "tzr'ansistox insert --198--.

001.11, true line 4 4 (appearing as line 45), cancel "24" and insert -23--.

Col. 13, line 22, after "the" insert --source--.

C01. 14, line 2, cancel "through the" (second occurrence).

Signed and sealed this 18th day of January 1972.

(SEAL) .Attest:

EDWARD M.FLETCHER, JR. ROBERT GOTTSCHALK Attesting Officer Acting Commissioner of Patents 

1. A circuit for controlling current flow through a resistive load from an alternating current source comprising: a synchronizing circuit including a transistor having an input connected to the source and an output connected to supply an output signal at each instant the alternating current of the source reverses, a timing means having an input connected to receive the output signal from the synchronizing circuit and provide an output signal a preselected time interval during each half cycle of alternating current flow subsequent to the receipt of an output signal from the synchronizing circuit, and firing means having an input connected to receive the output signal from the timing means and provide output signals for alternately switching a pair of power circuit type silicon-controlled rectifiers that are connected in inverse parallel between the source and the load into conductive states in response to an output signal from the timing means, said firing means including, a pair of output signal pulsing circuits with a first of said pair of pulsing circuits including a first capacitor, a first silicon-controlled rectifier having a pair of main electrodes and a gate electrode, a first transformer having a primary winding connected in a series circuit with the first capacitor and the main electrodes of the first silicon-controlled rectifier and a secondary winding coupled through a magnet iron core to the primary winding and connected to the gate electrode and the cathode of a first one of the pair of power circuit type siliconcontrolled rectifiers, and a circuit including a diode and the primary winding of the first transformer for charging the first capacitor from the source with a pulse of current that flows in one direction through the primary winding of the first transformer when a first side of the source has a positive polarity, a second of said pair of pulsing circuits including, a second capacitor, a second silicon-controlled rectifier having a pair of main electrodes and a gate electrode, a second transformer having a primary winding connected in a series circuit with the second capacitor and the main electrodes of the second silicon-controlled rectifier and a secondary winding coupled through a magnet iron core to the primary winding and connected to the gate electrode and the cathode of a second one of the pair of power circuit type silicon-controlled rectifiers, and a circuit including a diode and the primary winding of the second transformer for charging the second capacitor from the source with a pulse of current that flows in one direction through the primary winding of the second transformer when a second side of the source has a positive polarity, and a commutating circuit means including a transistor having its conductive state controlled by the output signal from the timing means and connected to the gate electrodes of the siliconcontrolled rectifiers in the first and the second pair of pulsing circuits for switching the first silicon-controlled rectifier to a conductive state for discharging the first capacitor through the primary winding of the first transformer in a direction opposite the said one direction and thereby providing a firing pulse to the first power circuit type silicon-controlled rectifier when the second side of the source has a positive polarity and for switching the second silicon-controlled rectifier to a conductive state for discharging the second capacitor through the primary winding of the second transformer in a direction opposite the said one direction and thereby providing a firing pulse to the second power circuit type silicon-controlled rectifier when the first side of the source has a positive polarity.
 2. A circuit for controlling current flow through a resistive load from an alternating current source comprising; a synchronizing circuit including a transistor having an input connected to the source and an output connected to supply an output signal at each instant the alternating current of the source reverses, a timing means having an input connected to receive the output signal from the synchronizing circuit and providing an output signal a preselected time interval during each half cycle Of alternating current flow subsequent to the receipt of an output signal from the synchronizing circuit, a firing means having an input connected to receive the output signal from the timing means and providing output signals for switching a triac-type semiconductor device that has a pair of main electrodes connected in a series circuit between the and the load into a conductive state in response to the output signals from the timing means, said firing means including, a transformer having a first primary winding, a second primary winding and a secondary winding wound on a common core with the secondary winding connected between one of the main terminals and a gate electrode of the triac, a pair of pulsing circuits with a first of said pair of pulsing circuits including, the first primary winding, a first capacitor, a first silicon-controlled rectifier having a gate electrode and a pair of main electrodes, a circuit excluding the first primary winding and including a diode for charging the first capacitor from the source with a pulse of current when a first side of the source has a positive polarity, and a circuit including the first capacitor, the first primary winding and the main electrodes of the first silicon-controlled rectifier for discharging the first capacitor through the first primary winding and the first silicon-controlled rectifier with a current flow tending to saturate the core in one direction upon conduction of the first silicon-controlled rectifier, a second of said pair of pulsing circuits including, the second primary winding, a second capacitor, a second silicon-controlled rectifier having a gate electrode and a pair of main electrodes, a circuit excluding the second primary winding and including a diode for charging the second capacitor from the source with a pulse of current when a second side of the source has a positive polarity, and a circuit including the second capacitor, the second primary winding and the main electrodes of the second silicon-controlled rectifier for discharging the second capacitor through the second primary winding and the second silicon-controlled rectifier with a current flow tending to saturate the core in a direction opposite the said one direction upon conduction of the second silicon-controlled rectifier, and circuit means including a transistor having its conductive state controlled by the output signal from the timing means and connected to the gate electrodes of the silicon-controlled rectifiers in the said first and the second pair of pulsing circuits for switching the first silicon-controlled rectifier to a conductive state for discharging the first capacitor through the through the first primary winding and causing the secondary winding to provide a pulse of current between the gate and the said one main terminal of the triac that flows in one direction when the second side of the source has a positive polarity and for switching the second silicon-controlled rectifier to a conductive state for discharging the second capacitor through the second primary winding and causing the secondary winding to provide a pulse of current between the gate and the said one main terminal of the triac that flows in a direction opposite the said one direction when the first side of the source has a positive polarity.
 3. The circuit as recited in claim 1 wherein the synchronizing circuit includes an actuatable means connected to the input of the transistor to prevent the synchronizing circuit from supplying the output signal when the actuatable means is deactivated.
 4. The circuit as recited in claim 1 wherein the gate electrode of the first silicon-controlled rectifier is connected through a first diode to the second side of the source and the gate electrode of the second silicon-controlled rectifier is connected through a second diode to the first side of the supply and said first and second diodes being connected to the transistor in the commutating circuit and poled in a direction to cause the first silicon-controlled rectifier to Switch to a conductive state when the first side of the source has a negative polarity and to cause the second silicon-controlled rectifier to switch to a conductive state when the second side of the source has a negative polarity.
 5. The circuit as recited in claim 2 wherein the synchronizing circuit includes an actuatable means connected to the input of the transistor to prevent the synchronizing circuit from supplying the output signal when the actuatable means is deactivated.
 6. The circuit as recited in claim 2 wherein the gate electrode of the first silicon-controlled rectifier is connected through a first diode to the second side of the source and the gate electrode of the second silicon-controlled rectifier is connected through a second diode to the first side of the supply and said first and second diodes being connected to the transistor in the commutating circuit and poled in a direction to cause the first silicon-controlled rectifier to switch to a conductive state when the first side of the source has a negative polarity and to cause the second silicon-controlled rectifier to switch to a conductive state when the second side of the source has a negative polarity.
 7. The circuit as recited in claim 1 wherein the timing means includes a pair of timing circuits which are selectively programmed so that the timing means will provide an output signal at either of two different time intervals during each half cycle subsequent to the receipt of an output signal from the synchronizing circuit.
 8. The circuit as recited in claim 2 wherein the timing means includes a pair of timing circuits which are selectively programmed so that the timing means will provide an output signal at either of two different time intervals during each half cycle subsequent to the receipt of an output signal from the synchronizing circuit. 